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0 ... 125126127128129130131 ... 233 . Protel 99 SE. 8 - , GAL16V8. . . - WAITGEN.SI. , , , WAITGEN.ABS, . WAITGEN.ABS . WaitGen: Name Partno Date Revision Designer Company Assembly Location WaitGen; P9000183; 07/16/87; 02; Osann; ATI; PC Memory; g20v8; /* This device generates chip select signals for one * /* 8Kx8 ROM and two 2Kx8 static RAMs. It also drives * /* the system READY line to insert a wait-state of at * /* least one cpu clock for ROM accesses * ****************************************************** ORDER: cpu clk, %2, al5, %2, al4, %2, al3, %2, al2, %2, all, %2, Imemw, %2, imemr, %2, reset, %2, !oe, %4, !ram csl, %2, !ram cs0, %2, !rom cs, %2, waitl, %2, wait2, %2, ready; VECTORS: /* 123456-leave six blanks to allow for numbers in .SO file */ $msg " Power On Reset OXXXXXlllO HHH**Z $msg " Reset Flip Flops CXXXXXllOO HHHLLZ $msg " Write RAMO 0001000100 HLHLLZ $msg " Read RAMO 0001001000 HLHLLZ $msg " Write RAMI 0001010100 LHHLLZ $msg " Read RAMI 0001011000 LHHLLZ $msg " Begin ROM read 0000001000 HHLLLL $msg " Two clocks for wait state, Then drive READY High $repeat2; COOOOOIOOO HHL*** $msg " End ROM Read 0000001100 HHHHHZ $msg " End ROM Read COOOOOllOO HHHLLZ : , ORDER VECTORS. WAITGEN.SI , WAITGEN.PLD, . WAITGEN.PLD WAITGEN.SI , . : Name Partno Date Revision Designer Company Assembly Location WaitGen; P9000183; 07/16/87; 02; Osann; ATI; PC Memory; U106; * This device generates chip select signals for one */ /* 8Kx8 ROM and two 2Kx8 static RAMs. It also drives */ /* the system READY line to insert a wait-state of a */ /* least one cpu clock for ROM accesses */ ORDER WAITGEN.PLD, . , . . CPU CLK, . . . "%" . , , , ! !RAM CS1 - : ORDER: CPU CLK, %2, 15, %2, 14, %2, 13, %2,12, %{N/Dƈ+bߡwQ1=t(QB eފ=m`0 /֭G` |
